TASK MANAGEMENT CASCADE ARBITER Russian patent published in 2023 - IPC G06F13/378 

FIELD: task prioritization.

SUBSTANCE: invention relates to a cascading task manager arbiter. The device contains N channels for processing tasks, an external bus for the input request IP and N external tires for channel parameters IC1, IC2, …, ICN, which consist of L groups of channel parameters, the external priority bus of the input IPR request, which comprises m bits of setting the priority rank (where m=] log₂M [(] [ is a larger integer), M is the number of priority ranks, the highest rank priority has the highest number (M-1), N external buses of priorities of channels IV1, IV2, …, IVN, (lowest priority has the lowest first channel), N internal priority buses of channels BV1, BV2, …, BVN, N bits of the internal bus S of the state of the channels S1, S2, …, SN, a group of N external channel indicator outputs QU1, QU2, …, QUN of lower priority in the unitary code 1 of N, external ready flag QF and external status flag QFS, and also comprises a group of N parameter analysis blocks 1₁, 1₂, …, 1_N, each of which comprises a group of L comparators 2₁, 2₂, …, 2_L and element AND 3, a group of N priority resolution blocks 4₁, 4₂, …, 4_N, each of which comprises a group of m elements OR with inverse input 5₁, 5₂ …, 5_m, input priority comparison comparator 10, decoder 11, NOR element 12, and also comprises Z cascades of priority comparison blocks 6_IJ, each I-th stage comprises N/2^I priority comparison blocks 6_IJ (where Z =] log ₂ N[(] [ is the larger integer); I is the cascade number, where I=2, 3,… Z; J is the number of priority comparison block in the I-th cascade, where J=1, 2,… , N/2^I), each block comparing priorities 6_IJ comprises a comparator 7, the first multiplexer 8 priority and the second multiplexer 9 of the channel number.

EFFECT: identifying a processing channel with a minimum priority rank and comparing it with the priority rank of the input task.

1 cl, 1 dwg, 1 tbl