FIELD: computer technology.
SUBSTANCE: invention relates to the field of computer technology. The device contains an external input request bus IP and N external bus parameters of channels IC1, IC2, …, ICN, which consist of L groups of channel parameters, N external busses of channels IT1, IT2, …, ITN, which each contain M bits of priority rank ( the highest priority rank has the lowest zero digit, the highest priority has the highest channel ITN), the external bus of channel numbers MK, the external input of the IK mode, the first group of N external outputs of the channel indicators of the highest priority QU1, QU2, …, QUN, the second group of M external outputs of indicators of the highest priority rank in the channel OZ0, OZ1, …, OZ(M-1) and an external ready flag QF, as well as N internal request buses IZ1, IZ2, …, IZN, internal status buses S1 channels, S2, …, SN, channel readiness K1, K2, …, KN and priority U1, U2, …, UN, internal flags FK and FU, as well as parameter analysis group 11, 12, …, 1N, each of which contains a group of comparators 21, 22, …, 2L and element AND 3, a group of request resolution blocks 41, 42, …, 4N, each of which contains the first group of elements AND 50, 51, …, 5(M-1), the first group of elements OR 60, 61, …, 6(М-1), the second group of prohibition elements AND with inverse inputs 71, 72, …, 7(M-1), a group of blocks for analyzing the readiness of channels 81, 82, …, 8N, each of which contains the third group of elements AND 91, 92, …, 9(M-1) and the first OR element 10, as well as the second OR element 11, the third OR element 12, the AND element 13, the group of INE elements 141, 142, …, 14N, the fourth group of AND elements with inverse inputs 151, 152, …, 15(N-1), multiplexer 16 and group of multiplexers 171, 172, …, 17N.
EFFECT: providing the possibility of simultaneous selection of several channels.
1 cl, 1 dwg, 1 tbl
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Authors
Dates
2022-08-11—Published
2021-12-01—Filed