PARALLEL STRUCTURE TASKS MANAGER ARBITER Russian patent published in 2023 - IPC G06F13/378 

FIELD: computer technology.

SUBSTANCE: invention can be used for arbitration in multiprocessor information processing systems for parallelizing the flow of applications. The device comprises N channels for processing tasks, an external bus for the input request IP and N external tires for channel parameters IC1, IC2, …, ICN, external priority bus of the input request IPR, N external priority buses of channels IK1, IK2, …, IKN, N internal priority buses of channels BZ1, BZ2, …, BZN in the unitary code "1 of M", internal buses of priority ranks BV, multi-bit single code of low priority BW, input priority in unitary code BPR, channels of low priority VK, as well as a group of N blocks of parameter analysis 1₁, 1₂, …, 1_N, a group of N decoders 4₁, 4₂, …, 4 _N, input priority decoder 5, groups of OR elements, groups of prohibition elements AND with inverted inputs, group of N blocks for analysis of channel readiness 8₁, 8₂, …, 8_N, AND elements, groups of AND elements, OR elements and an OR-NOT element.

EFFECT: expansion of functionality in terms of the possibility of parallel detection of a processing channel with a minimum priority rank and comparison with the priority rank of the input task.

1 cl, 1 dwg, 1 tbl