FIELD: manufacture of integrated circuits. SUBSTANCE: procedure involves shaping of IC components and low-level wiring buses on semiconductor substrate, application of interlevel dielectric, pyrolytic deposition of layer of polycrystal silicon or silicon nitride, its anisotropic removal in plasma up to exposing interlevel dielectric, application of second layer of dielectric and formation of contacts. Proposed technique ensures planarization of surface due to filling side recesses and cavities upon forming low-level wiring. EFFECT: improved planarization of surface, eliminated high-temperature treatment. 3 cl, 4 dwg
