FIELD: microelectronics. SUBSTANCE: process includes covering semiconductor plate surface having dielectric layer and contact cut with first conducting layer, shaping part of first capacitor plate in it, depositing isolating layer, applying photoresist mask with contact cut pattern, opening the contact cut, removing photoresist mask, applying second conducting layer contacting first one through contact cut, forming other part of capacitor first plate in it, selectively removing isolating layer, forming capacitor dielectric, applying third conducting layer, producing second capacitor plate in it. Novelty is that isolating layer is deposited upon application of first conducting layer, second conducting layer and additional isolating layer are applied, photoresist mask is deposited, and self-aligned cut is opened to interconnect conducting layers at the same time forming part of first capacitor plate in lower conducting layers, then photoresist mask is removed, connecting conducting layer is formed, additional surface pattern of first plate is shaped by photolithography, isolating layers are selectively removed, and capacitor dielectric is formed on naked surface and in additional conducting layer. EFFECT: improved yield of integrated circuits, improved quality of the latter due to reduced troubles. 2 cl, 5 dwg, 1 tbl
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Authors
Dates
1998-05-10—Published
1990-10-15—Filed