METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE Russian patent published in 2001 - IPC

Abstract RU 2176423 C2

FIELD: electronic engineering. SUBSTANCE: device has capacitor structure on metal. Method involves forming accumulating contact member in the area of cells matrix and metal contact member for making intermediate interconnection in the area of peripheral circuit at the same time. Discharge bus is connected to active zone of semiconductor sublayer. The semiconductor sublayer has transistor mounted in the area of cells matrix and peripheral circuit. It is covered with dielectric films separating current-conducting layers. The first protective layer is formed from the first electric insulating material for coating discharge bus on the produced structure. The first dielectric film separating current-conducting layers is formed on the whole surface of the produced structure to expose the upper surface of the first protective layer by using the second insulation material having ratio of itching velocities differing from that of the first insulation material. The second protective layer is created from the third electric insulation material on the first protecting layer and the first dielectric film separating current-conducting layers. The first contact window for placing the accumulating contact member electrically bound with active zone of semiconductor sublayer and the second contact window for placing metal contact member for making local interconnection are sequentially formed in the area of peripheral circuit and cells matrix by means of photolithography. Then, electric conducting layer is formed by metal precipitation all over the whole surface of the created structure for filling the first and the second contact windows. A pin is formed in the first contact window by removing current-conducting layer in the area of the peripheral circuit. Then, the second dielectric film separating current-conducting layers is formed from the fourth electric insulation material in the area of the peripheral circuit of the created structure. Etching rate ratio of the fourth electric insulation material differs from that of the third one. Accumulating electrode is produced from the first current-conducting material in the area of cells matrix on the upper part of the pin. Then, dielectric film is formed on the electrode surface and flat electrode from the second current-conducting material is formed on it. EFFECT: simplified production process. 6 cl, 10dwg

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RU 2 176 423 C2

Authors

Li Dzho-Jang

Kim Ki-Nam

Dates

2001-11-27Published

1997-04-28Filed