FIELD: semiconductor microelectronics. SUBSTANCE: integrated circuit has insulating plate bearing metallization layout pattern and provided with depressions to receive chips of chip semiconductor devices secured therein by means of adhesive. Face side of chips carrying contact pads is in same plane as plate surface and contact pads of chips are electrically connected to metallization layout pattern. Depressions have tilted walls Wall-to-plate-surface tilting angle (α) is 90.1 to 150 deg. for chip size of 0.5 x 0.5 x 0.15 mm and depression size of 0.6 x 0.6 x 0.16 mm. EFFECT: enhanced reproducibility of electrical characteristics; facilitated manufacture. 3 cl, 4 dwg
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Authors
Dates
2002-06-10—Published
1996-10-10—Filed