METHOD FOR PRODUCING INSULATION OF SMALL-SCALE INTEGRATED CIRCUIT COMPONENTS Russian patent published in 2004 - IPC

FIELD: microelectronics.

SUBSTANCE: method includes following operations: forming regions of first and second polarities of conductivity, epitaxial layer, and insulating layers on silicon substrate of first polarity of conductivity; etching slots in epitaxial and buried layers, and in substrate through depth equal to width of depleted charge in bottom part of buried-layer-to-substrate p-n junction affording vertical position of etched slots; forming insulating layers on vertical walls of slots; doping slot bottom with impurity of same polarity of conductivity as substrate; filling slot with layer at reduced pressure, its thickness being dependent on desired structure topography found from formula h_l = Ѕ(L²/4d + d), where h_l is thickness of deposited layer; L is slot thickness; d is structure topography; planarizing deposited layer by chemical and mechanical polishing and plasmachemical etching to make it planar with slot; producing passive and active components of small-scale integrated circuit in insulated regions using known methods. Desired topography is formed on wafer by evaporating layer of optimal thickness at reduced pressure with reduced number of open circuits in evaporate metal.

EFFECT: reduced process cycle time; enhanced yield.

1 cl, 2 dwg