FIELD: technologies for microelectronics. SUBSTANCE: method involves generation of p-type areas, reverse channel and dielectric insulation areas on silicon substrate, deposition of first layer of polysilicon, generation of first layer of silicon oxide and generation of polysilicon masks with holes for gate areas, etching first layer of polysilicon through mask holes down to substrate, generation of second layer of silicon oxide in faces of first layer of polysilicon in mask holes, generation of under-gate layer of silicon oxide, deposition of second layer of silicon oxide, deposition of layer of phosphor-silicate glass over second layer of silicon oxide, melting said layer of glass, etching phosphor-silicate glass by means of plasma-chemical methods in order to achieve planar structures with respect to second layer of polysilicon, etching second layer of polysilicon by means of plasma-chemical methods in order to achieve planar structures with respect to first layer of polysilicon, etching first and second layers of silicon oxide by means of plasma-chemical methods in order to achieve planar structures with respect to second layer of polysilicon, generation of source and drain areas and electrodes to these areas, generation of metal wiring. The goal of invention is achieved by use of anisotropy etching. EFFECT: increased density of MOSFETs, decreased number of photolithographic operations. 8 dwg
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Authors
Dates
1996-05-10—Published
1986-02-14—Filed