METHOD TO MANUFACTURE FIELD TRANSISTORS WITH SELF-ALIGNED GATE OF SUBMICRON LENGTH Russian patent published in 2011 - IPC H01L21/338 

FIELD: electricity.

SUBSTANCE: in the method to manufacture GaAs field transistors with a self-aligned gate of submicron length a channel of n-type conductivity is made by means of ion alloying of semi-insulating substrates of gallium arsenide with single-charge ions of silicon, four layers of silicon oxide are deposited, being different in composition, with various speed of liquid etching, at the same time the layers with higher and lower speed of liquid etching are alternated, a multi-layer dielectric mock-up of the gate is formed by reactive-ion etching of dielectric layers so that a part of thickness of the first layer of dielectric remains on the surface, afterwards the column is etched with simultaneous removal of the remained part of the first layer, and the following procedures are carried out: ion alloying of contact areas of source and drain with the help of two inclined implantations using the mock-up of the gate as a self-aligning element, high-temperature activation annealing, planarisation of the surface by a photoresist, reactive ion etching of the photoresist, replacement of the multilayer dielectric mock-up for the metal gate, and ohmic contacts are made.

EFFECT: increased voltages of gate-drain breakthrough due to formation of a structure with low-alloyed drain and source, reduced defectiveness brought into the near-surface layer of the channel, development of the possibility to form the electrode of larger height gate due to production of the optimal profile of the dielectric gate mock-up.

4 cl, 12 dwg