DEVICE FOR PROTECTING LEADS OF COMPLEMENTARY MOS (METAL-OXIDE-SEMICONDUCTOR) INTEGRATED CIRCUITS ON SOS (SILICON-ON-SAPPHIRE) AND SOI (SILICON-ON-INSULATOR) STRUCTURES FROM STATIC ELECTRIC DISCHARGES Russian patent published in 2012 - IPC H01L27/02 

FIELD: physics.

SUBSTANCE: invention relates to semiconductor industry. In the device for protecting leads of complementary MOS integrated circuits on SOS and SOI structures from static electric discharges, the lead of the contact pad (1) is connected to lateral diodes D (2) and D (3), the drain of transistor T (4) and internal electrode circuits (10), lateral diodes D (2) and D (3), anode d (2) and cathode D (3) are connected to the input bus, the cathode D (2) is connected the positive power (8) bus, and the anode D (3) is connected to the earth (9) bus, the drain (source) of an n-channel transistor T (4) is connected to the input bus, the source (drain) is connected to the earth (9) bus, and the gate is connected to the earth bus through a resistor R (5), between the power bus (8) and the earth bus (9) there is an n-channel transistor T (6) whose gate is connected to the earth bus through a resistor R (7). The lateral diodes are formed in isolated islands of the epitaxial structure, have a developed (long) perimetre of the boundary of the p-n junction away from the contacts to the current carrying buses and do not have a gate over lightly doped regions of the base, and n-channel transistors have ring gates which are connected to the earth bus through high-ohmic resistors; regions of the channels of the transistors are not connected to fixed potentials.

EFFECT: invention provides fast passage of current without damaging epitaxial islands when exposed to static electric discharge of up to 3500 V.

3 cl, 2 dwg