METHOD FOR MANUFACTURING OF MIS-NANOTRANSISTOR WITH LOCAL AREA FOR BURIED INSULATION Russian patent published in 2013 - IPC H01L21/336 B82B3/00 

FIELD: electricity.

SUBSTANCE: in method for manufacturing of MIS-nanotransistor with local area for buried insulation at surface of silicone substrate of the first type of conductivity an insulating layer is formed around active regions of the transistor, a groove is formed as a basis for a stepped relief; then the first near-wall region and layer mask is formed, implantation of ions, mainly of oxygen, is performed till a layer with high concentration of oxygen and silicone oxide atoms is formed; the second near-wall region is formed, then implantation of ions of the second type is made here components with atoms with higher oxides are used which form glass with silicon dioxide; while thin buried insulation layer and active drain and source regions are formed simultaneously by annealing at temperature higher than softening point but less than glass transition temperature; for the purpose of drains and source regions insulation from each other an isolation channel is formed and insulating layer is applied to its surface; terminating regions are formed.

EFFECT: manufacturing process that allows manufacturing of MIS-nanotransistors without use of high-resolution lithography with maximum reduction of short-channel effect.

1 ex, 4 dwg