MANUFACTURING METHOD OF SHF LDMOS TRANSISTORS Russian patent published in 2013 - IPC H01L21/336 

FIELD: electricity.

SUBSTANCE: in method of SHF LDMOS transistors manufacturing, including manufacturing of feed-through diffusive source p⁺-junctions of elementary transistor cells in high-ohmic epitaxial p^--layer of the source p^-p⁺-silicone substrate, growing of gate dielectric and formation of polysilicone electrodes for gate of elementary cells at the surface of high-ohmic p^--layer of the substrate, creation of p-wells for elementary cells in high-ohmic p--layer of the substrate by means of boron ion introduction into the substrate using polysilicone electrodes for the gate and photoresist coatings as a mask and subsequent diffusive redistribution of the introduced additive; when p-wells are made gate dielectric between polysilicone electrodes for the gate of elementary cells is reduced to thickness of 100-300 Ǻ, to the substrate face the first protective photoresist coating is applied, two gaps in the first protective photoresist coating are opened simultaneously respectively at the place of heavy-alloyed n⁺-regions of drain and source of the elementary cells and phosphorus ions are introduced through them with dose of 0.2-0.6 mcC/cm and energy of 80-140 keV and arsenic ions with dose of 400-500 mcC/cm and energy of 40-80 keV; then the second drain gap is opened and phosphorus ions are introduced through it in the same dose and energy as to the first drain; then the third drain gap is opened and phosphorus ions are introduced through it with less dose and energy in comparison with the second drain; then next grades of lightly-alloyed n^--drain regions of elementary cells are formed in similar way. Phosphorus ions are implanted to the next grade with a less dose and energy in comparison with the previous one; thereafter remainders of protective photoresist layer are removed from the substrate face and simultaneous up-diffusion of the introduced additives of phosphorus and arsenic is made.

EFFECT: creating method for manufacturing of powerful silicone SHF LDMOS transistors with reduced transistor cell spacing, improved frequency and energy parameters and higher percent of fit structures output.

7 dwg, 1 tbl