FIELD: information technologies.
SUBSTANCE: memory flash element includes a semiconductor substrate with a source and a drain formed in it, and the following components serially arranged on the substrate between the source and the drain: a tunnel layer, a memorising layer, a blocking layer and a conducting gate, besides, the memorising layer is made in the form of a solid inert conducting layer from tantalum nitride TaN or titanium nitride TiN, the lower limit of the memorising layer thickness is limited by the possibility of existence of the solid layer, and the upper limit - by desire to reduce effect of interference and value of parasitic capacitance.
EFFECT: reduced parasitic capacitance between floating gates of adjacent flash elements of memory and prevention of erasure of information on adjacent flash elements of memory.
9 cl, 1 dwg
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