FIELD: process engineering.
SUBSTANCE: invention relates to electronic engineering. Production of multiple chip 3D IC by vertical assembly with the help of TSV technology comprises forming of through copper conductors in chips on silicon plate that have ledges abode face or rear side of thinned plates. Simultaneously with etching of deep vertical holes in silicon deep vertical grooves are etched in chip boundaries to fill their walls with metals with similar ledges. Through vertical conductors and through heat sink frames on plates are simultaneously connected. Note here that space between chips is sealed to up the chips bond strength. System of heat removal from every chip and the entire assembly is created.
EFFECT: complete electric shielding of multichip assembly, decreased width of gaps between chips to approx micrometers.
11 cl, 23 dwg
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