FIELD: electricity.
SUBSTANCE: invention is referred to manufacturing technology of multilevel metallisation for very large integrated circuits (VLIC). The method for manufacturing of multilevel copper metallisation for VLIC with multiple repetitions of processes for manufacturing of standard structures consisting of copper horizontal and vertical conductors and surrounding dielectric layers with low value of effective dielectric constant includes application of metal layers to semiconductor plate, photolithography, local electrochemical application of copper and protective layers to its surface. The manufacturing process includes three stages performed in sequence: manufacturing of horizontal copper conductors, manufacturing of intralayer porous dielectric insulation with ultralow value of dielectric constant and intralayer insulation made of solid dielectric and manufacturing of vertical copper conductors.
EFFECT: invention ensures non-availability of integrated process operations, improved mechanical strength of conductors due to placement of copper conductor inside solid dielectric.
14 cl, 18 dwg
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