METHOD OF MAKING MULTILEVEL METALLISATION OF INTEGRATED MICROCIRCUITS WITH POROUS DIELECTRIC LAYER IN GAPS BETWEEN CONDUCTORS Russian patent published in 2012 - IPC H01L21/768 

FIELD: physics.

SUBSTANCE: method of making multilevel conductor paths of integrated microcircuits with a porous dielectric layer in gaps between conductors involves forming a first conducting and a first dielectric layer, making holes in the first dielectric layer, forming a second conducting layer on the surface with filling of the holes, chemical-mechanical polishing of a second conducting layer, resulting in formation of multilevel vertical conductors, forming a mask, local etching of the first dielectric layer and the first conducting layer and removing the mask, resulting in formation of horizontal conductors separated by gaps, forming a second protective dielectric layer, forming a third porous planarising dielectric layer, plasma etching of the surface of dielectric layers selectively to the material of the vertical conductors, forming a fourth dielectric layer with the surface level higher than the surface level of the vertical conductors, chemical-mechanical polishing of the surface until opening of the vertical conductors, repeating the cycle until obtaining the required number of conducting levels, forming the top level of horizontal conductors and passivation.

EFFECT: faster operation, higher reliability and output of nondefective articles, broader functional capabilities of manufacture thereof.

12 cl, 20 dwg