FIELD: electricity.
SUBSTANCE: invention relates to semiconductor microelectronics and nanoelectronics and can be used in designing logic integrated circuits with elements of nanometer size. In the OR-NOT integrated logical element based on single-layer three dimensional nanostructure, containing the first and the second logical transistors, load resistor and a substrate, logical structure is nanosized with a stepped profile.
EFFECT: new thin-layer OR-NOT integral logical element based on layered three dimensional nanostructure with vertically oriented layers where “base-emitter” and “base-collector” working transitions are surface transitions with low power consumption and minimum transition surfaces, reduced power consumption and faster operation due to reduced parasitic capacitance of transitions.
1 cl, 13 dwg
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