FIELD: physics, computer engineering.
SUBSTANCE: to create integrated circuits with memory components of nanometer dimensions. The essence of invention is that the bistable memory cell based on a single-layer nanostructure with horizontally oriented strata comprises a dielectric substrate, the first and the second logic transistors, the first and the second load diodes placed on the dielectric substrate, and is made nanoscale with stepped profile where the working transitions "base-emitter", "base-collector" of two transistors are surface transitions with low power consumption and the lowest transition surfaces.
EFFECT: possibility is provided to reduce power consumption while increasing the performance by reducing parasitic capacitances of working transitions.
8 dwg
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