HIGH-POWER MICROWAVE FIELD TRANSISTOR ON SEMICONDUCTOR HETEROSTRUCTURE Russian patent published in 2016 - IPC H01L29/80 

FIELD: electricity.

SUBSTANCE: invention relates to microwave electronic equipment, namely to powerful field transistors on the semiconductor heterostructure. In a powerful microwave field transistor on the semiconductor heterostructure comprising a semiconductor substrate and a sequence of at least one layer of a wide and one of a narrow-bandgap material of the semiconductor heterostructure with specified characteristics and electrodes of source, gate, drain made according to the given topology of the field-effect transistor, the said semiconductor heterostructure is made in the form of a sequence of at least one buffer layer of GaAs, a group of conducting layers, which form the FET channel, as part of the channel layer of In_yGa_1-yAs of at least two delta-doped with a donor dopant of δn-layers and of two not alloyed with the admixture of spacer i-layers of Al_xGa_1-xAs in pairs located on both sides of the channel layer, two groups of barrier layers of Al_xGa_1-xAs, each in the form of a system of barrier layers, one of which is located on one side of the group of conducting layers - the substrate one, the other one - on the opposite side - the gate one, herewith the substrate group of barrier layers is made as an acceptor-donor i-p-i-δn system of barrier layers of Al_xGa_1-xAs, the gate group of barrier layers is in the form of a donor-acceptor δn-i-p-i system of barrier layers of Al_xGa_1-xAs, herewith the adjacent δn-layer doped with the donor dopant of each group of barrier layers is simultaneously the δn-layer doped with the donor dopant, for the corresponding group of conducting layers, a gate electrode is planar on the external not doped with the admixture of Al_xGa_1-xAs i-layer of the gate group of barrier layers, or is planar in any other possible layer of the semiconductor heterostructure above the latter, source and drain electrodes are made each in the corresponding additionally formed recess in the semiconductor heterostructure, herewith the bottom of each said recess is located level with the lower border of a doped with an acceptor dopant p-layer of the gate group of barrier layers or below in any other layer of the semiconductor heterostructure down to the semiconductor substrate.

EFFECT: provided are higher output power, gain and efficiency.

4 cl, 3 dwg, 1 tbl