PIXEL BLOCK WITH THIN-FILM TRANSISTOR MADE OF LOW-TEMPERATURE POLYCRYSTALLINE SILICON AND METHOD FOR MANUFACTURE THEREOF Russian patent published in 2018 - IPC H01L21/77 

FIELD: manufacturing technology.

SUBSTANCE: use to manufacture a pixel block with a thin-film transistor made of low-temperature polycrystalline silicon. Essence of the invention consists in the fact, that method of manufacturing a pixel block with a thin-film transistor of low-temperature polycrystalline silicon comprises: preparing the substrate and forming a buffer layer on the substrate; forming a layer of a semiconductor structure and a first insulating layer having the same thickness, and with their location in the same layer; the step of forming the buffer layer on the substrate includes the step of: sequentially forming a layer of silicon nitride and a layer of silicon oxide on the substrate; the step of forming a layer of a semiconductor structure and a first insulating layer on the buffer layer located in the same layer and having the same thickness includes the steps of: forming amorphous silicon layer on the buffer layer and performing the crystallization process of the amorphous layer to form a polycrystalline silicon layer; structuring the amorphous silicon layer by the first photolithography process to form a semiconductor structure layer; forming a layer of silicon nitride, the thickness of which coincides with the thickness of the layer of the semiconductor structure, on the layer of the semiconductor structure and the buffer layer where no layer of the semiconductor structure is formed; applying a negative photoresist on the silicon nitride layer in places that do not coincide with the location of the semiconductor structure layer; structuring silicon nitride layer by a second photolithography process; etching the silicon nitride layer on the semiconductor structure layer to etch the silicon nitride layer from the semiconductor structure layer to form the first insulation layer, the thickness of which coincides with the thickness of the layer of the semiconductor structure at both edges of the layer of the semiconductor structure.

EFFECT: providing the possibility of reducing the side effect and improving electrical properties.

10 cl, 3 dwg