FIELD: instrument engineering.
SUBSTANCE: invention relates to the field of design and production of power semiconductor devices and, mainly, silicon voltage limiters. In the proposed method, conditions are created for complete isolation, both on the surface and on the side cut of the metallization layers, metals, ohmic contacts of crystals when etching a damaged silicon layer.
EFFECT: technical result of the invention is the creation of a method of manufacturing crystals of power semiconductor devices with a flat pn-junction, precluding the use of precious and toxic metals, as well as the deposition of metal atoms of ohmic contacts on the pn-junction during etching the disturbed silicon layer from the side surface of the crystal formed after the separation of silicon wafers with pn structures into crystals, id est reducing the parasitic leakage current pn-junction.
1 cl, 1 tbl, 6 dwg
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Authors
Dates
2018-12-07—Published
2017-10-30—Filed