FIELD: physics.
SUBSTANCE: invention relates to multilayer stack (10) of semiconductor chips with several semiconductor chips (11) arranged in multilayer assembly (18) and with at least one connecting substrate (19), which connects semiconductor chips (11) to each other, wherein semiconductor chips (11) at least on one edge (12) of the chip are provided with at least one attachment surface of the chip, which at least partially extends as side connection surface (13) in side surface (23) of semiconductor crystal made on edge (12), and wherein side surfaces (23) of semiconductor chips (11) provided with side connection surface (13) are located in common plane S of side surfaces of multilayer arrangement (18) of semiconductor chips, and wherein connecting substrate (19) with contact surface (20) is located parallel to plane S of side surfaces of semiconductor chips (11) and for connection of connection conductor structure (31) made in connection substrate (19) has connection surfaces (21) of substrate made on contact surface (20), which in parallel contact surface (20) of connection plane VI, electrically conductive by means of binding material are connected to side connection surfaces (13).
EFFECT: disclosed is a multilayer arrangement of semiconductor chips, as well as a semiconductor chip for making such multilayer arrangement of 5 semiconductor chips.
14 cl, 8 dwg
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Authors
Dates
2022-05-18—Published
2018-06-05—Filed