METHOD FOR COMPARATIVE EVALUATION OF THE RESISTANCE OF BATCHES OF INTEGRATED CIRCUITS TO ELECTROSTATIC DISCHARGE Russian patent published in 2023 - IPC G01R31/26 

FIELD: integrated circuits testing.

SUBSTANCE: invention relates to the testing of integrated circuits (IC) and can be used to determine the resistance of batches of IC to electrostatic discharge (ESD) in the manufacture of electronic equipment. Mechanical tests of the IC are carried out, which are permissible according to the technical conditions, by repeated blows to the IC leads. After mechanical testing, random samples from IC lots are divided into at least three groups of ICs, the ICs of each group are subjected to ESD until the IC fails, and the number of discharges applied to the ICs is determined. ESD is supplied to one group of ICs with a voltage of at least twice the maximum allowable according to specifications. The other group of ICs is supplied with ESD with an increased voltage of 100-300 V compared to the first group. Next, the ESD voltage is again increased by 100-300 V to affect the next group of ICs in the sample. Then the average number of ESD impacts on the IS of each group is determined. According to the largest value of the average number of ESD impacts, the resistance of the IC batch to ESD is estimated as higher.

EFFECT: increasing the reliability of the assessment of the comparative reliability of IC.

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