METHOD FOR COMPARATIVE EVALUATION OF THE RESISTANCE OF BATCHES OF INTEGRATED CIRCUITS TO ELECTROSTATIC DISCHARGE Russian patent published in 2023 - IPC G01R31/303 

FIELD: microelectronics.

SUBSTANCE: invention relates to the control of semiconductor integrated circuits (IC). Each IC from representative samples from each batch being compared is exposed to electrostatic discharges (ESD) of different polarity with a voltage equal to twice the value allowed by specifications for a given type of IC until the IC fails. The ICs of subsequent samples from the compared batches are exposed to the ESD potential increased by a certain amount, for example, 250 V, until the IC fails. The procedure with increasing ESR potential is repeated at least two times. Then dependencies are plotted for the sample-averaged values of the number of ESD pulses before until the IC fails exposed to the ESD voltage. The IC batch with the lower dependence obtained is assumed to be more resistant to ESD than the other batch.

EFFECT: increased reliability of resistance assessment of IC batches to ESD.

1 cl, 1 dwg, 1 tbl