GALLIUM ARSENIDE DIFFERENTIAL STAGE WITH AN AMPLIFICATION STEEPNESS MULTIPLIER Russian patent published in 2023 - IPC H03F3/34 

FIELD: radio engineering and communication.

SUBSTANCE: the invention relates to radio engineering and communication, and may be used as an amplification element and transformation of analog signals in the structure of gallium arsenide chips for various functional purposes, including “servicing” IP modules in power amplifiers. Gallium arsenide differential stage with amplification steepness multiplier, the input multiport (1) on gallium arsenide transistors with the first (2) and the second (3) potential inputs, as well as the first (4) and the second (5) current output matched with the first (6) power supply bus, the first (7) and the second (8) current outputs of the device, and the common source circuit (9) of the input multiport (1) on gallium arsenide transistors is coordinated with the second (10) power supply bus. The first current output of the input multiport is connected with the gate of the first (11) additional field-effect transistor and the gate of the second (13) additional field-effect transistor. A drain of the second (13) additional field-effect transistor is connected with the first (7) current output of the device, and its source is connected to the drain of the first (11) additional field-effect transistor. The second (5) current output of the input multiport (1) on gallium arsenide transistors is connected to the gate of the third (14) additional field-effect transistor and through the second (15) additional resistor is connected to the source of the third (14) additional field-effect transistor and the gate of the fourth (16) additional field-effect transistor. The drain of the fourth (16) additional field-effect transistor is connected to the second (8) current output of the device, and its source is connected to the drain of the third (14) additional field-effect transistor, the sources of the second (13) and third (14) additional field-effect transistors are connected to the input (17) of an additional non-inverting cascade (18), the output of which (19) is connected to the gates of the fifth (20) and sixth (21) additional field-effect transistors. The drain of the fifth (20) additional field-effect transistor is connected to the gate of the first (11) additional field-effect transistor, the drain of the sixth (21) additional field-effect transistor is connected to the gate of the third (14) additional field-effect transistor, and the sources of the fifth (20) and sixth (21) additional field-effect transistors are connected to the bias voltage source (22).

EFFECT: increasing the differential stage in the amplification steepness, in which the input multiport (1) can have dozens of modifications and work with small static currents of GaAs transistors.

3 cl, 9 dwg