FIELD: microelectronics; production of MIS highly integrated circuits. SUBSTANCE: gate with vertical walls is formed on surface of silicon semiconductor plate of first type of conductivity, nondoped silicon dioxide layer is applied to stepped-profile surface, layer applied is removed by anisotropic plasma etching to create wall dielectric regions, slowly diffusing and then quickly diffusing dope of second type of conductivity are introduced in turn by ion implanting on either side of wall regions into plate, highly doped and lightly-doped source-drain regions are produced by annealing introduced dope. EFFECT: improved yield and speed of MIS transistor due to reduced capacity. 2 dwg, 1 tbl
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Authors
Dates
1996-10-10—Published
1991-06-26—Filed