FIELD: microelectronics, design of integrated circuits with elements of submicron and nanometric dimensions, especially when high density of elements is required. SUBSTANCE: two-gate MIS structure with vertical channel has substrate of certain type of conductance with column which side surface is coated with dielectric layer where two gates are positioned and drain is located in top of column and source. Type of conductance of upper layer of substrate and column is opposite to that of base of substrate. Conductance of column is close to inherent conductance of semiconductor. Gates are placed on opposite side parts of column and drain is manufactured in the form of junction "metal tunnel dielectric-semiconductor". EFFECT: provision for high density of arrangement of elements. 1 dwg
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Authors
Dates
1998-03-10—Published
1995-07-04—Filed