TRANSISTOR WITH CURRENT LIMITATION AND METHOD OF ITS MANUFACTURING Russian patent published in 2009 - IPC H01L29/772 

FIELD: electric engineering.

SUBSTANCE: invention is related to power vertical transistors, comprising MOS-structure, produced with application of double diffusion, having source electrodes (emitter) and gate on one surface of substrate, and drain electrode (collector) on opposite surface of substrate. In transistor with current limitation, comprising substrate having the first and second opposite surfaces, DMOS-transistor installed on the first surface of substrate, alternating areas of N-type and P-type of conductivity arranged on the second surface of substrate, cells of DMOS-transistor on the first surface of substrate have a shape of strips, alternating areas of N-type and P-type of conductivity have a shape of strips on the second surface of substrate, moreover, strips on the second surface of substrate are arranged perpendicularly relative to strips on the first surface of substrate. In process of transistor manufacturing they form areas of N-type and P-type of conductivity on the second surface of substrate with a certain ratio of areas.

EFFECT: manufacturing of transistor of increased resistance to short circuit of load circuit with specified current limitation, increased accuracy of reproducibility of specified current limiter, increased yield of good transistors in percentage ratio, reduced prime cost of transistors manufacturing.

7 cl, 1 dwg