FIELD: calculating; counting.
SUBSTANCE: invention relates to the computer equipment. Memory device with resistance variation contains a semiconductor substrate; provided on semiconductor substrate transistor with control output, first output and second output; a first insulating layer covering the transistor and comprising a first material; a second insulating layer provided on the first insulating layer and comprising a second material other than the first material; a third insulating layer provided on the second insulating layer and comprising a first material; a first contact rod penetrating the first insulating layer and connected to the first terminal; first and second conductive lines; resistance change element provided in first insulating layer and connected between second terminal and second conductive line; a second contact rod provided in the first insulating layer and connected between the resistance change element and the second conductive line; and a third contact rod provided in the first insulating layer and connected between the resistance change element and the second terminal.
EFFECT: technical result consists in prevention of reading and writing errors.
5 cl, 40 dwg
Title | Year | Author | Number |
---|---|---|---|
SEMICONDUCTOR MEMORY DEVICE | 2014 |
|
RU2642960C2 |
METHOD FOR WRITING IN MRAM-BASED MEMORY DEVICE WITH REDUCED POWER CONSUMPTION | 2011 |
|
RU2546572C2 |
MAGNETIC MEMORY AND METHOD OF MANAGEMENT OF IT | 2014 |
|
RU2628221C1 |
RECORDING OPERATION FOR MAGNETORESISTIVE RANDOM ACCESS MEMORY WITH SPIN TRANSFER TORQUE WITH REDUCED SIZE OF BIT CELL | 2009 |
|
RU2471260C2 |
SEMICONDUCTOR STORAGE DEVICE | 2015 |
|
RU2681344C1 |
CONTROL OF WORD LINE TRANSISTOR SIGNAL LEVEL FOR READING AND RECORDING IN MAGNETORESISTIVE RAM WITH TRANSFER OF SPIN TORQUE | 2008 |
|
RU2419894C1 |
SPIN TRANSFER TORQUE MAGNETORESISTIVE RANDOM-ACCESS MEMORY AND DESIGN METHODS | 2008 |
|
RU2427045C2 |
SPIN-TORQUE TRANSFER MAGNETORESISTIVE MRAM MEMORY ARRAY INTEGRATED INTO VLSIC CMOS/SOI WITH n+ AND p+ POLYSILICON GATES | 2012 |
|
RU2515461C2 |
ARRAY STRUCTURAL DESIGN OF MAGNETORESISTIVE RANDOM ACCESS MEMORY (MRAM) BIT CELLS | 2009 |
|
RU2464654C2 |
MEMORY DEVICE BASED ON CHANGE IN RESISTANCE | 2014 |
|
RU2620502C2 |
Authors
Dates
2019-10-07—Published
2016-03-14—Filed