FIELD: semiconductor technology.
SUBSTANCE: present invention relates to a memory cell and a method for its manufacture, as well as a storage device and a method for its manufacture. The memory unit includes a first dielectric layer and a second dielectric layer, which are stacked. The first dielectric layer houses the first transistor. The second transistor is placed in the second dielectric layer. The first dielectric layer is connected to the second dielectric layer via a connecting wire. The parasitic capacitance in the first transistor or the second transistor is used as a memory element to replace a capacitor in the related art, so that the volume occupied by the memory cells can be reduced to ensure that the memory cells are developed in the embedding direction. In addition, the first transistor and the second transistor are both metal oxide thin film transistors.
EFFECT: memory device can have a longer charge retention time to improve the performance of the memory device while reducing the volume of the memory device.
10 cl, 10 dwg
