FIELD: microelectronics. SUBSTANCE: method involves coating metallized integrated circuit surface with layer of silicon dioxide by plasma-chemical method followed by application of film-forming alcohol solution of tetraethoxysilane, annealing at 100-150 C while heating on substrate side to form planarizing layer of silicon dioxide, plasma-chemical etching of this layer, applying second layer of silicon dioxide; novelty is that film-forming solution is applied at substrate temperature of 40-60 C and annealing is carried out while heating at a rate of 0.2-0.3 c/min. EFFECT: improved planarization quality due to eliminating cracks and exfoliation of silicon dioxide layers.
| Title | Year | Author | Number |
|---|---|---|---|
| METHOD OF MAKING MULTILEVEL METALLISATION OF INTEGRATED MICROCIRCUITS WITH POROUS DIELECTRIC LAYER IN GAPS BETWEEN CONDUCTORS | 2011 |
|
RU2459313C1 |
| METHOD FOR PRODUCING BIPOLAR-TRANSISTOR INTEGRATED CIRCUITS | 1988 |
|
SU1538830A1 |
| METHOD OF SMOOTH PATTERN PRODUCTION ON INTEGRATED CIRCUITS | 1990 |
|
SU1766214A1 |
| PROCESS OF MANUFACTURE OF TWO-LEVEL COATING | 1991 |
|
RU2025825C1 |
| METHOD FOR MANUFACTURING PROGRAMMABLE MEMBERS | 2003 |
|
RU2263370C2 |
| PROCESS OF FORMATION OF MULTILEVEL INTERCONNECTIONS OF INTEGRATED MICROCIRCUITS | 1991 |
|
RU2028696C1 |
| MANUFACTURING METHOD OF MULTI-LEVEL COPPER METALLISATION OF VLSIC | 2010 |
|
RU2420827C1 |
| PROCESS PLANATION OF INTEGRATED CIRCUITS | 1992 |
|
RU2024992C1 |
| PROCESS OF MANUFACTURE OF SELF-ALIGNED BUILT-IN COPPER METALLIZATION OF IN TEGRATED CIRCUITS | 2002 |
|
RU2230391C2 |
| METHOD TO MANUFACTURE MULTI-LEVEL INTERCONNECTIONS OF INTEGRAL MICROCIRCUIT CHIPS WITH AIR GAPS | 2010 |
|
RU2436188C1 |
