MANUFACTURING PROCESS FOR MULTILEVEL INTERCONNECTIONS OF INTEGRATED CIRCUITS Russian patent published in 1996 - IPC

FIELD: microelectronics; manufacture of superlarge-scale integrated circuit with two levels of metal deposition. SUBSTANCE: process involves creation of first level of aluminium base interconnections on semiconductor plate with formed active regions, deposition of interlevel silicon dioxide base insulating layer, mask formation on its surface for opening contact cuts, plasma etching of insulation, mask removal, deposition of metal layer, and creation of upper level of interconnections on it; mask for opening contact cuts is made in the form of double-layer system by applying vanadium layer, 0.08-0.12 mcm thick, and photoresist layer, 1.5-2.2 mcm thick; insulation etching is conducted in plasma C₃F₈ at pressure of 60-180 Pa and power density of 0.1-0.3 W/sq. cm for time period chosen from equation d_max/v_etch≅ t ≅ 1,75d_min/v_etch, where d_max, d_min is maximum and minimum thickness of interlevel insulation, respectively; v_etch is rate of etching of interlevel insulation. EFFECT: improved yield due to elimination of level-to-level short circuits; elimination of not contact between levels.